Complementary metal-oxide semiconductors (CMOS) are a major class of integrated circuits (ICs). CMOS chips include microprocessors, microcontrollers, static RAM, and other digital logic circuits. An advantage of CMOS technology is that it only uses significant power when its transistors are switching between on and off states. Consequently, CMOS devices use significantly less power and produce less heat than other forms of logic devices. CMOS technology also allows a high density of logic functions on a chip. In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as silicon (Si).
Generally CMOS processing includes forming multiple shallow trench isolation (STI) regions in a top layer of a substrate. The STI regions are typically formed to isolate, for example, a silicon on insulator (SOI) device region or an electronic component area in an SOI substrate, from another device region. The SOI device region may be formed by selectively implanting p-type or n-type dopants into the semiconductor layer. A plurality of wells, e.g., P-wells, N-wells, can also be formed in the device region. For example, a P-well is formed of a P-type semiconductor material, and an N-well is formed of an N-type semiconductor material. A series of P-wells and/or a series of N-wells can be formed in the SOI substrate. It is noted that the N-type device region is typically used when a pFET channel is to be subsequently formed, while a P-type device region is typically used when an nFET channel is to be subsequently formed.
The STI regions are formed utilizing processing steps that are known to those skilled in the art including, for example, trench definition and etching, optionally lining the trench with a diffusion barrier, and filling the trench with a trench dielectric such as an oxide. After the trench fill, the structure may be planarized and an optional densification process step may be performed to densify the trench dielectric.
Currently, various oxides and nitrides are used as the STI dielectric material. As CMOS processing scales smaller, shallow trench isolation (STI) dimension needs to be reduced, resulting in poorer isolation (well to well, or junction to well) which may result in high leakage, or electrical breakdown.
Additionally, there are two types of isolation in a CMOS circuit. Inter-well STI isolates two different wells (between an N-well and a P-well), and intra-well STI isolates devices within a well (within an N-well or within a P-well). Although deeper STI trenches give better isolation, the depth of inter-well STI trenches needs to stay within the well boundary to maintain electrical connection of the well.
It would therefore be desirable to provide a method to create wider and deeper inter-well and intra-well isolation without negatively impacting circuit density. It would also be desirable to provide different size inter-well and inter-well STI trench isolation without negatively impacting circuit density. It would further be desirable to enhance performance of a CMOS chip/wafer without significantly increasing the cost of manufacturing while creating wider and deeper inter-well and intra-well STI trenches.